Cisco® CCNA Exam Cram Notes : Architectural Components of a Router

II. Cisco IOS

1. Cisco Router Architecture

1.2 Architectural Components of a Router

1.2.1 Processor

The CPU used here is typically Motorola 68030 CISC. The following are the important characteristics of the CPU.

32 bit bus, 20 MHz clock (25 MHz on some platforms).

256 Bytes internal Data Cache, 256 Bytes internal Instruction Cache, both direct mapped.

1.2.2 System Control Logic

System Control Logic is used to help the main processor with device control, interrupt handling, counting and timing, data transfer, minimal First In, First Out (FIFO) buffering, and communication with network interfaces and Dynamic RAM (DRAM).

1.2.3 Buses

CPU use Buses to access various components of the system. In addition, Buses are used to transfer instructions and data to or from specified memory addresses.

CPU Bus: It is used for high speed operations with direct Processor access.

System Bus: This allows communication with Ethernet/Token Ring controllers, WAN port interfaces, and so on.

1.2.4 Dual UART

Dual Universal Asynchronous Receiver-Transmitter (UART) provides the necessary user interface. It has one RS232 port, Data Communications Equipment (DCE) (for Console port) RJ45, and Data Terminal Equipment (DTE) (for Auxiliary port) RJ45.

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